Fabless chip design company Primemas presents customers the world’s first CXL 3.0 SoC

Passionategeekz On June 25, Fabless chip design company Primemas announced yesterday that it will issue customers the world’s first CXL 3.0 (based on PCIe 6.0 PHY) controller/main SoC.

Primemas’ CXL SoC adopts Hublets modular core/chip design. In addition to basic functional IP, it is also equipped with high bandwidth, low latency inter-chip interconnection interfaces, which can achieve seamless resource sharing with adjacent modules, which meansOne SoC can aggregate multiple CXL SoC modules。

Hublet with 1×1 design supports EDSFF up to 512GB DRAM capacity E3.S device; and PCIe AIC or CEM products with up to 2TB DRAM capacity in a 2×2 configuration;For higher 4×4 configurations, it can be connected to a 1U rack with a total DRAM memory capacity of up to 8TB.。

Jay Kim, Executive Vice President and Head of Business Development at Primemas, said:

We were inspired by the initial partners’ challenges leveraging Hublets to address the challenges of fast-growing workloads.

We are excited to take an important next step towards commercialization through collaboration with Micron and its CXL AVL (Passionategeekz Note: ASIC Verification Laboratory) program.

Luis Ancajas, Director of Business Development at Micron CXL, said:

With the rapid application of artificial intelligence and the corresponding increase in memory-intensive workloads, CXL-based solutions are driving innovation that transforms traditional computing platforms.

As an industry leader in data center memory solutions, we are excited to partner with innovators like Primemas to validate and accelerate next-generation solutions like Hublet SoC with our AVL program and help bring these transformative solutions to market, bringing data center performance, scalability, and efficiency to the next level.

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