Intel executives: In the future, chip manufacturing will reduce dependence on ASML high-NA EUV lithography machines, and instead enhance the core position of etching technology

Passionategeekz On June 21, according to the discussion content disclosed by investment research platform Tegus, an anonymous Intel director said that in the future, transistor design will reduce its dependence on advanced lithography equipment and instead enhance the core position of etching technology.

He believes that with the development of new structures such as fully surround gate field effect transistors (Passionategeekz Note: GAAFET) and complementary field effect transistors (CFETs), the overall demand for lithography in high-end chip manufacturing will weaken.

The current chip manufacturing process:

• Lithography link: ASML extreme ultraviolet (EUV) and high numerical aperture (High NA) lithography machine transfers circuit design to wafer

• Post-treatment link: Adding materials through a deposition process, and then selectively removing materials through an etching process to form a transistor structure

The Intel director stressed that the three-dimensional transistor structures such as GAAFETs and CFETs require “wrap the gate from all directions”, making the lateral removal of excess material a key, “Manufacturers will focus more on removing materials through etching processes rather than extending wafer processing time in lithography machines to reduce feature sizes.”

For the current technical solution, the most mainstream is the fin field effect transistor (FinFET), which connects the insulating material to the bottom of the transistor, so that the current can pass through the gate to complete control; the new design mainly includes:

Intel director said this three-dimensional structure allows chip manufacturing to “reduce dependence on the smallest feature size because not only high density can be achieved on the plane, but also through vertical stacking”, so the importance of high numerical aperture lithography machines in advanced processes “will be lower than the key position of current EUV devices in 7nm and more advanced technology nodes.”

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